1. Technical Field of the Invention
This invention relates to dynamic random access memories (DRAM). More particularly, it relates to capacitive mis-match sensing of bit-lines in a DRAM.
2. Background Art
In the operation of DRAM (Dynamic Random Access Memory) devices, it is required to maintain data stored in a charge storage cell of an array for a maximum retention period without performing a refresh operation in order to offer high availability and low power consumption. When competing with Static RAM (SRAM) devices, it is also desirable to offer high performance with the same DRAM design.
In the current state of the art there are DRAM designs that offer either high retention times for the stored data or high performance.
A conventional DRAM sensing scheme is known as half-VDD sensing, in which both the true and complementary bit-lines are pre-charged to a value approximately halfway between a logic 1 voltage (VDD) and a logic 0 voltage (ground, or GND). When a cell is coupled to a pre-charged bit-line, the voltage will then slightly increase or decrease, depending on the value of the bit stored in the cell, thus creating a differential voltage with respect to the complementary bit-line and VDD/2.
However, for performance reasons, a ground sensing scheme pre-charges the bit-line pair to ground prior to a read operation. Because of the pre-charging to ground, reference word lines are needed to place a reference voltage (e.g., (Vread1-Vread0)/2) on either the bit-line or the complementary bit-line in order to be able to read a 0 bit.
Additionally, in order to reduce the effects of capacitance between adjacent bit-line pairs, a given bit-line pair is twisted at various locations along the length of the bit-line. Generally, even numbered bit-line pairs are twisted at different locations with respect to adjacent odd numbered bit-line pairs. For example, the even numbered bit-line pairs might be twisted just once at ½ of the total length, while the odd numbered pairs are twisted at ¼ of the total length, and again at ¾ of the total length.
Unfortunately, the use of bit-line twisting complicates the reference word-line schemes, in that reference cells for each region are required.
Both bit-line twisting and reference cells require area and adversely impact DRAM macro efficiency. Consequently, there is a need in the art for a a GND pre-charge scheme that does not require twisting or reference cells.
Referring to FIG. 1, under control of clock and control circuitry 88, a conventional mid-level sense amplifier system 58 pre-charge the bit-lines BTX and BCX to mid-level potentials VREFX, such as VDD/2, VDD/3, or VDD/X (where VDD is power supply voltage and X is a number greater than 1, and offer good retention times for the data stored in array 54. Rail sensing schemes pre-charge the true and complementary bit-lines BTX and BCX to VDD or ground (GND) and offer good performance. Data read from array 54 under control of clock and control 88 by sense amp 58 is typically stored to a local buffer 60 for transfer to digital circuits 62.
Both of the rail sensing (VDD or GND pre-charge) systems typically require reference cells that require area.
Referring to FIG. 2, an example of a CMOS negative field effect transistor (NFET) circuit 61 comprises a gate 63, a drain (connection to circuitry) 65, and a source (connection to ground) 67. In operation, as the voltage on gate 63 goes higher than the voltage on drain 65 by some threshold voltage, NFET 61 turns on, shorting source 67 to drain 65.
Referring to FIG. 3, an example of a CMOS positive field effect transistor (PFET) circuit 71 comprises a gate 73, a drain (connection to circuitry) 77, and source 75 to voltage VDD. In operation, as the voltage on gate 73 falls below the voltage on source 75 by some threshold voltage, PFET 71 turns on, shorting source 75 to drain 77.
Referring to FIG. 4, memory arrays 54 are composed of rows 40 and columns 42, and typically include one transistor 48 as a switch and one capacitor 50 as a storage element. A single cell 52 is accessed by decoding one row 40 and one column 42 in matrix 54. A row, or word-line, 44 connects storage capacitor 50 to columns, or bit-line 46, and storage capacitor 50 transfers charge to bit-line 46, thus altering bit-line voltage.
Referring to FIG. 5, a change in bit-line 46 voltage is amplified with a cross coupled sense amp 38, which compares bit-line voltage with a reference 47, such that (bit-line voltage)−(reference)=(signal). A positive signal amplifies to logical ‘1’, and a negative signal amplifies to logical ‘0’. Differential voltage is amplified by a cross coupled pair of transistors N0, N1, connected as shown between bit-line (BL) 46 and reference voltage (BL-not) 47 and set node 56. When set node 56 voltage is less than [(V+ΔV)−Vtn1] (where Vtn1 is the threshold voltage of transistor N1) on BL 46, current will start to flow across transistor N1 from not-BL 47 to set node 56. This is referred to as “on-side conduction”. When set node 56 voltage is less than [(V)−Vtn0] (where in Vtn0 is the threshold voltage of transistor N0), then current will start to flow from BL 46 to set node 56 across transistor N0. This is referred to as “off-side conduction”. Off-side conduction is modulated by set speed and amount of signal, and complimentary X-couple pairs provide full CMOS levels on bit-line 46.
When one uses a GND sensing scheme during the pre-charge time, all the bit-lines of the DRAM array 54 are pre-charged to GND. Although a GND pre-charge sensing scheme can support a wider operating range and provides more overdrive during amplification and more pre-charge than conventional VDD/2 sensing, it has the problem that it consumes more power. When considering signal development, charge transfer does not begin until the word-line voltage is greater than the bit-line voltage by the amplitude of a threshold voltage (Vt). This is critical for a longer word-line that will have significant slew rate, e.g. a 1 Volt/nanosecond slew introduces an extra 750 picosecond delay for VDD/2 pre-charge (equal to about 1.5V). Although GND sense circuits require reference cells (1.5% 16 Megabyte area), they also offer static and dynamic bit-line balancing and provide an excellent interlock for sense amplifier timing generation. However, a GND pre-charge scheme suffers from the problem of degraded retention characteristics for a stored ‘1’, where the drain to source voltage of the storage transistor is the worst case for leakage current through the storage transistor.
When one stores a data value of “1” on the storage node of a deep trench capacitor 50 of a memory cell 52, the drain-source voltage is at the level of the supply potential VDD. During the pre-charge mode, the leakage through the weak channel of the cell transistor 48 is strongly dependent on both the gate-source voltage 52 and the drain 46-source GND voltage. Therefore, in a GND sensing scheme, the retention characteristic for a data value of “1” is degraded.
Alternatively, if a VDD sensing scheme is employed for a DRAM, the data value of “0” data retention characteristic of a data value of “0” is degraded by a large degree of leakage. To compensate for such a large degree of leakage, more frequent refresh operations are needed, but frequent performance of a refresh operation has dual disadvantages. The first disadvantage is that data retention functions consume excessive power required to refresh the memory cell. The second disadvantage is that memory availability is degraded because it is inaccessible during the time consumed by performance of the increased number of refresh cycles.
Therefore, both of the above GND and VDD sensing schemes, which present the problem of high cell leakage during the pre-charge condition, are not suitable for low power applications, even if such schemes show better performance and design robustness regardless of power supply voltage.
Use of mid-level sensing such as VDD/2 or VDD/X (where X is a number greater than 1) provides better cell leakage characteristics. With a mid-level sensing scheme, the data retention characteristic of a data value of “1” is improved because the gate-source voltage of the cell transistor is negative. The degree of data retention of a data value of “0” is also better than that for a VDD sensing scheme because source-drain voltage of the cell transistor is dropped from VDD to (VDD−VDD/2 or VDD/X). Also, the degree of data retention of a data value of “0” is not an issue because another leakage source compensates for the cell channel leakage from the bit-line to the storage node of the storage capacitor. Although mid-level sensing offers better retention characteristics, performance thereof falls short of objectives.
Barth et al. (hereinafter, Barth) discovered and described in U.S. patent application Ser. No. 10/906,471, filed 22 Feb. 2005, entitled “Bi-Mode Sense Amplifier With Dual Utilization of the Reference Cells and Dual Pre-charge Scheme for Improving Data Retention Time,” that a solution to this problem is to retain the benefits of each of the above-described sensing schemes.
Accordingly, the Barth invention employs hybrid pre charge schemes wherein a bit-line level is switched from mid-level during a self-refresh, data retention mode of operation to a GND or a VDD sensing scheme during a mission mode of operation. Thus, Barth describes a dual pre-charge scheme including two operation modes which are the mission mode and the data retention mode. The mission mode is a real data access mode. The data retention mode is just to keep the data without sending or receiving data while running as a low power mode. The bit-line pre-charge level during the mission mode of operation is the same as required for the sensing scheme regardless of pre-charge or active mode. However, during the self-refresh, data retention mode, the bit-line pre-charge level is maintained around VDD/X (VREFX), making the gate-source voltage (VDD/X) and reducing the voltage drop across the cell transistor 48.
Sense amplifiers are described in J. E. Barth et al. “Embedded DRAM design and architecture for the IBM 0.11-m ASIC offering” IBM J. RES. & DEV. VOL. 46 NO. 6 pages 675-689 (November 2002).
Noise phenomenon include external noise (wire or Sx), and line to line coupling.
Referring to FIG. 6, external noise at sense amp 38 is reduced to common mode by folding BL 46 with respect to not-BL 47.
Referring to FIG. 7, line to line coupling is limited by bit-line twisting of bit-lines A 81, B 83, with respect to not-A 82 and not-B 84, respectively, as is represented at 80, 85, and 86, such that bit-line A 81 couples equally into bit-line B 83 and not-B line 84. Other forms of noise are introduced by local process variations which effectively degrades signals, Vt and )L mis-match, which is limited by longer channel length, overlay mis-alignment, which is limited by identical orientation, and capacitive mis-match, which is limited by careful physical design (symmetry).
Referring to FIGS. 8 and 9, in a conventional DRAM array of N cells, even word-lines couple N/2 cells to a true bit-line (BTx) 100, 122, and odd word-lines couple N/2 cells to a complementary bit-line (BCx) 102, 124. Isolation devices, controlled by ISO0 106 and ISO1 118, allow for sense amps 58 to be shared between upper 51 and lower 53 arrays.
Equalize phase (EQP0, EQP1) 104, 120 control the pre-charge of the bit lines BT0, BC0, BT1, and BC1.
Isolator gates (ISO0, ISO1) 106, 118 selectively isolate bit lines from amplifier 94, with unselected bit lines being isolated.
Equalize phase (EQP) 114 control the pre-charge of the sense amplifier 58.
Set N signal (SETN) 116 energize a set node signal, which is the common node for the cross coupled amplifier 94.
Column select, or bit switch, (BSN) 108 is a column multiplexor gating the data from sense amplifier 58 to the local buffers 60 via the data path FT 110 and FC 112.
Table 1 shows the state of the ISO and EQP signals of FIGS. 8 and 9 for various operations.
TABLE 1CONVENTIONAL ISO/EQP OPERATIONISO0EQP0ISO1EQP1Pre-ChargeX1X1Activate Upper100XActivate Lower0X10
Clock and control circuitry 88 provides timing and control signals to sense amplifier 58, including EQP0 104, ISO0 106, EQP 114, set node (SETN) 116, BSN 108, ISO1 118 AND EQP1 120. Data read from arrays 51, 53 is written to local buffer 60 for transfer to digital circuitry 62 (FIG. 1).
Sense amplifier 58 includes several functional components, including upper array isolate and pre-charge 90, column decode 91, pre-charge 92, set device 93, cross coupled sense amplifier 94, and lower array isolate and pre-charge 95.
Referring to FIG. 9, upper array isolate and pre-charge 90 includes NFET devices 130, 132, 134, and 136. True bit-line BT0 100 is connected to the drains of NFETs 130 and 134, complementary bit-line BC0 102 is connected to the drains of NFETs 132 and 136. The sources of NFETs 130 and 132 are connected to ground. EQP0 104 is connected to the gates NFETs 130 and 132, and ISO0 106 is connected to the gates of NFETs 134 and 136.
Column decode 91 includes PFETs 140 and 142, with their gates connected to BSN 108. The drain of PFET 140 is connected by line 301 to the source of NFET 134 and the drain of PFET 142 is connected by line 307 to the source of NFET 136. The sources of PFETs 140 and 142 are connected to local buffer 60 via nodes FT 110 and FC 112, respectively.
Pre-charge 92 includes NFETs 144, 146, and 148. The sources of NFETs 144 and 148 are connected to ground, and their drains to the source of NFET 134 on line 301 and NFET 136 on line 307, respectively. NFET 146 is coupled between the drains of NFETs 144 and 148 at x and y, respectively. EQP 114 is connected to the gates of NFETs 144, 146, 148.
Set device 93 includes PFET 150 and NFET 152. The source of PFET 150 is connected to logic voltage level VDD, source of NFET 152 is connected to ground, and their drains are coupled together by line 305. SETN 116 gates PFET 150 and EQP gates NFET 152.
Cross coupled sense amp 94 includes PFET devices 160 and 162 and NFET devices 164 and 166. The sources of PFETs 160 are connected to line 305 at the coupled drains of FET devices 150, 152. The sources of NFETs 164 and 166 are connected to ground. The drains of FET devices 160 and 164 are connected via line 301 to the sources of NFETs 134 and 170 and to the gates of FET devices 162 and 166. The drains of FET devices 162 and 166 are connected by line 307 to the sources of NFETs 136 and 172 and to the gates of FET devices 160 and 164.
Lower array isolate and pre-charge 95 includes NFET devices 170, 172, 174, and 176. The source of NFET 170 is connected by line 301 to the source of NFET 134, and to the drains of FET devices 140, 144, 160, 164, to the gates of FET devices 162, 166, and to node X of NFET 146. The drain of NFET 170 is connected to the drain of NFET 174 and true bit-line BT1 122 to the lower array 53. The source of NFET 172 is connected by line 307 to the source of NFET 136 and to the drains of FET devices 142, 148, 162, 166, to the gates of FETs 160, 164, and to node Y of NFET 146. The drain of NFET 172 is connected to the drain of NFET 176 and complemen bit-line BC1 124 to the lower array 53. The sources of NFETs 174 and 176 are connected to ground. IS01 118 gates NFETs 170 and 172, and EQP1 120 gates NFETs 174 and 176.
Referring to FIG. 10, in operation sense amplifier system 58 in step 180 starts in the pre-charge state where EQP 104, EQP0 114 and EQP1 120 are held high by control circuitry 88. SETN 116 is held inactive in the high state, and isolation gates ISO0 106 and IS01 118 held low. Column select BSN 108 is held inactive in the high state.
In step 182, the first part of activation is to take amplifier 58 out of pre-charge by lowering EQP 114 and one of EQP0 OR EQP1, controlled by a high order address. The falling edge of EQP 114 turns off FETs 144, 146, 148, 152.
In step 184, the second part of activation is to address one of arrays 51 or 53 and taken it out of pre-charge. This is done, for example for the top array 51, by taking EQP0 low, turning off FETs 130 and 132, and simultaneously activating ISO0 106 to turn on FETs 134 and 136.
Continuing with respect to top array 51 (as is shown by Table 1, the operation for lower array 53 is analogous), in step 186 a word and a reference word are activated in upper array, developing differential signals on nodes BT0 100 and BC0 102. That differential signal is passed through NFETs 134 and 136 to bit-line nodes ST 301 and SC 307.
In step 188, the differential signal at nodes ST and SC is then amplified by activation of SETN 116 going low, turning on PFET 150. That will energize the cross coupled amplifier formed by FETs 160 162 164, 166. These will amplify the differential signal to a logic level VDD and in step 190 the result is transferred to digital circuits FT and FC via PFETs 140 and 142 upon activation of column select BSN 108.
In step 192, when the activation cycle of steps 186-190 is complete, the word line 52 in the selected array (in this case, array 51) is turned off, thus trapping the charge in the DRAM cell 52 (FIG. 4) of array 51.
In step 194, the amplifier system 58 is pre-charged by charging bit-lines BT0 100 and BC0 102 to ground via FETs 130, 132 upon the activation of EQP0 104. EQP 114 is also activated, thus returning the system to the pre-charge state of step 180.